1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits, and, more particularly, to integrated circuits including nonvolatile memory devices.
2. Description of the Related Art
Nonvolatile memory, such as, for example, flash memory, may be used in various storage devices, such as, for example, secure digital memory cards (SD cards), USB sticks, solid state drives (SSDs), and internal memory of various electronic devices, such as, for example, mobile phones, tablet computers, media players, etc. Further applications of nonvolatile memory include embedded systems, such as microcontrollers, wherein a nonvolatile memory device may be integrated on a same semiconductor structure as other circuitry of a microcontroller, such as, for example, volatile memory, a CPU and/or input/output devices.
Types of nonvolatile memory devices include split gate nonvolatile memory devices, which may provide advantages in reliability and performance over other types of nonvolatile memory, such as, for example, control gate nonvolatile memory.
Split gate nonvolatile memory devices are described, for example, in U.S. Patent Publication No. 2012/0241839 and U.S. Pat. Nos. 7,923,769, 7,732,278, 8,173,505 and 8,263,463.
Split gate nonvolatile memory devices may include a plurality of split gate nonvolatile memory cells, which are typically arranged in an array and are electrically connected to electrically conductive lines extending along columns and rows of the array. The electrically conductive lines may be used for programming, erasing and/or reading the split gate nonvolatile memory cells. Each split gate nonvolatile memory cell may include an active region formed in a semiconductor material, such as, for example, silicon. The active region may include a source region, a drain region and a channel region that is arranged between the source region and the drain region. The channel region may be doped inversely to the doping of the source region and the drain region. For example, the source and drain regions may be N-doped, and the channel region may be provided in a P-well that is provided in the semiconductor material, and may have a P-type doping corresponding to the doping of the P-well.
Above the channel region, a control gate electrode and a select gate electrode may be provided adjacent each other. Between the control gate electrode and the channel region, a nonvolatile memory stack may be provided, and a select gate insulation layer may be provided between the select gate electrode and the channel region. The select gate electrode may be arranged at the drain side of the channel region, and the control gate electrode may be arranged at the source side of the channel region. The nonvolatile memory stack may include a charge storage layer that may include silicon or silicon nitride and is separated from the control gate electrode and the channel region by isolation layers formed of an electrically insulating material, such as silicon dioxide.
Due to the electrical isolation of the charge storage layer that is provided by the isolation layers, electrical charge may be stored for a relatively long time in the charge storage layer, wherein the amount of charge in the charge storage layer may represent data stored in the split gate nonvolatile memory cell.
The select gate electrode and the control gate electrode may be electrically insulated from each other, wherein the electrical insulation between the select gate electrode and the control gate electrode may be provided by a portion of the nonvolatile memory stack, as described, for example, in U.S. Patent Publication No. 2012/0241839 and U.S. Pat. Nos. 7,923,769, 8,173,505 and 8,263,463, or by a sidewall spacer as described in U.S. Pat. No. 7,732,278.
For reading data from the split gate nonvolatile memory cell, the source region may be grounded, and relatively small positive voltages of, for example, about 1 V may be applied to the select gate electrode, the control gate electrode and the drain. The channel region between the source region and the drain region may be influenced by the electrical charges stored at the charge storage layer, so that a current that is representative of the data stored in the split gate nonvolatile memory cell flows between the drain region and source region of the split gate nonvolatile memory cell.
For programming split gate nonvolatile memory cells, a source side injection of charge carriers into the charge storage layer may be performed. For this purpose, the drain region of the split gate nonvolatile memory cell may be grounded, a relatively high positive voltage of, for example, about 4 V may be applied to the source region, and an even higher positive voltage, for example a voltage in a range from about 6-9 V, may be applied to the control gate electrode. A voltage slightly greater than the threshold voltage of the channel region of the split gate nonvolatile memory cell may be applied to the select gate electrode.
The split gate nonvolatile memory cell may be erased by Fowler-Nordheim tunneling. For this purpose, a negative bias may be applied between the control gate electrode and the source and drain regions. For example, a relatively high negative voltage of, for example, about −6 V may be applied to the control gate electrode, and a relatively high positive voltage of, for example, about 6 V may be applied to each of the source region and the drain region. A relatively high positive voltage of, for example, about 5 V may be applied to the select gate electrode.
Known split gate nonvolatile memory devices may have issues associated therewith. For example, in some split gate nonvolatile memory devices, the control gate electrode and the select gate electrode may be provided by polysilicon layers that partially overlap with each other. In this case, any misalignment of these layers may result in decreased performance and yield. Select gate insulation layers formed of silicon dioxide and select gate electrodes formed of polysilicon may provide limited possibilities for reducing the size of the split gate nonvolatile memory cells. Using portions of the nonvolatile memory stack for separating the select gate electrode and the control gate electrode may reduce the possibilities for reducing the size of the split gate nonvolatile memory cells. Moreover, split gate nonvolatile memory cell designs may have issues related to the integration of split gate nonvolatile memory cells with logic transistors that are provided in the same semiconductor structure.
In view of the situation described above, the present disclosure relates to a semiconductor structure and a method for the formation thereof, wherein some or all of the above-mentioned issues are overcome substantially completely or at least partially.